The present invention generally relates to phase-locked loops (PLLs) and, in particular, to an improved wideband phase-locked loop with adaptive frequency response.
FIG. 1 illustrates a conventional PLL. As shown in FIG. 1, the conventional 3rd order type II PLL architecture includes a phase-frequency detector (PFD), a charge pump (CP), a 2nd order loop filter, a voltage-controlled oscillator (VCO), and a feedback divider.
The gain of the PFD and CP (KPFD) is proportional to the charge pump maximum output current ICP. KVCO is the voltage-to-frequency gain of the VCO in units of Hz/V. The feedback divider has a gain of 1/M, where M is the modulus of the divider. This results in an open loop gain equation given by Equation (1).
                              H          ⁡                      (            jω            )                          =                                            (                                                jω                  ·                                      τ                    1                                                  +                1                            )                        ·                          K              VCO                        ·                          I              CP                                                                          (                jω                )                            2                        ·                          (                                                jω                  ·                                      τ                    2                                                  +                1                            )                        ·                          (                                                C                  1                                +                                  C                  2                                            )                        ·            M                                              Eq        .                                  ⁢                  (          1          )                    where: τ1=R1·C1; τ2=τ1·C2/(C1+C2)
Trying to design the blocks of the PLL to automatically handle a wide reference frequency range may present many problems. For example, one disadvantage of the foregoing architecture as shown in FIG. 1 is that when the reference signal changes, some aspect of the loop needs to change with the reference signal in order to shift not just the bandwidth but the stabilizing corners as well. Another disadvantage of this architecture is that in order to span a wide range of VCO frequencies (FVCO), KVCO needs to be large due to a limited control voltage range. However, a large KVCO forces the dominant pole capacitor to increase and the charge pump current to decrease, thereby increasing the PLL's sensitivity to charge pump noise, loop filter noise, and ripple caused by charge pump mismatches. Furthermore, in order to handle a wide range of M, the charge pump current is usually made programmable with M.
Self-tuning wideband PLL's have been generally known in the industry. In one prior art system, the self-biased PLL manipulates the charge pump gain by a modest switch network that adjusts the current gain by 1/M. However, a drawback of this approach is the complexity introduced by an additional feedback loop to compensate for KVCO which requires special attention with respect to stability and start-up conditions.
In another prior art system, the PLL incorporates a sampled proportion and integral path control. This PLL, however, utilizes a complicated method of frequency tracking that employs programming the proportional path gm and C as a function of input divider value N. This PLL also requires the programming of the integral path C as a function of M.
Hence, it would be desirable to provide an improved wideband PLL that is capable of, amongst other things, avoiding the disadvantages of prior art systems as described above.